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FUJITSU SEMICONDUCTOR MICROCONTROLLER
MB90M405
F2MC-16LX FAMILY 16-BIT MICROCONTROLLERS
HARDWARE MANUAL ABSTRACTS
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MB90M405 F MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL ABSTRACTS (c)1999 FUJITSU LIMITED Printed in Japan
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Circuit diagrams utilizing Fujitsu products are included as a mean of illustrating typical semiconductor applications. Complete information sufficient for construction proposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copy right, patent right to trademarks claimed and owned by Fujitsu. Fujitsu reserved the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The products described in this document are not intended for use in equipment requiring high reliability, such as marine relays and medical life-support systems. For such applications, contact your Fujitsu sales representative. If the products and technologies described in this document are controlled by the Foreign Exchange and Foreign Trade Control Act established in Japan, their export is subject to prior approval based on the said act.
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Preface n Objective of Manual and Target Audience The MB90M405 Series is a general-purpose semiconductor device in the F2MC-16LX family. It is a 16-bit single-chip microcontroller ASIC (Application Specific IC). This manual explains the functions and
operations of the MB90M405 Series for engineers who design products using this device.
How to Read This Manual n Page Organization A summary is given below the title of each section. A title of the main section is noted in the sub-section to recognize a current-reading section. n Index Organization (1) Register map index The register map index format is similar to the I/O map and it allows search for the page explaining the bits of each register from the address, register abbreviation, register name, and resource macro name. Use the register map index at searching for the register function when designing a resource macro. (2) Pin function index The pin function index is similar to the explanation of the pin function and it allows serch for the block diagram of each resource macro, the explanation of the pin function, and notes from the package pin number, pin name, circuit type, and resource macro name. Use the pin function index when creating the system board, etc. (The pin function index will be provided in the next revision of this manual). n Organization of Notes and Checks Notes Check : : Reference information is given here. Use this as a hint or note when using the MB90M405. This also gives a section(s) to refer. Precautions when using the MB90M405 are given here. Specification restrictions, etc., are included.
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1. GENERAL
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Features............................................................................ 1-3 Resources......................................................................... 1-4 Product Lineup .................................................................. 1-5 Block Diagram................................................................... 1-6 Pin Assignment ................................................................. 1-7 Pin Description .................................................................. 1-8 I/O Circuit Type ............................................................... 1-11 Notes on Handling Devices ............................................. 1-13 Clock Supply Map ........................................................... 1-15
1.10 Low Power Consumption Mode....................................... 1-16
MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-2
GENERAL
This chapter explains the features and basic specifications of the Monolith (MB90M405). The MB90M405 Series is a general-purpose 16-bit microcontroller developed for applications requiring fluorescent lamp panel control and contains 60 high-voltage withstand output pins required for a fluorescent lamp. As with the original F2MC-8L and F2MC-16L families, the instruction system inherits the AT architecture, and has extended high-level language interface instructions and the extended addressing modes, enhanced multiplication/division instructions (signed), and enhanced bit processing. In addition, a 32-bit accumulator enables handle long word processing.
1.1 Features
* Clock: * PLL Clock multiplication circuit built-in * Operating clock (PLL clock) generated by dividing original oscillation by 2 or by multiplying original oscillation by 1 to 4 (2.1 MHz to 16.8 MHz at original oscillation of 4.2 MHz). Can be selected. * Minimum instruction execution time is 59.5 ns (when the original oscillation is 4.2 MHz, the PLL clock is generated by multiplying the original oscillation by 4, and Vcc = 3 V). * It is possible to generate an external output as a clock output by dividing the original oscillation by 16, 32, 64, or 128. * Maximum memory space: 16 Mbytes * 24-bit addressing in memory space * Instruction system suited for controller * Applicable data types (bit, byte, word, long-word) * Various addressing modes: 23 types * High code efficiency * High-precision operation with 32-bit accumulator * Signed multiplication and division instructions and enhanced RETI instruction * Powerful instruction system applicable to high-level language (C) or multitasking * System stack pointer * Symmetric instruction set and barrel shift instruction * Program patch function (2-address pointer) * Shortened execution time: 4-byte instruction queue * Powerful interrupt function (eight programmable priority levels) * Powerful interrupt function for 32 interrupt factors * Data transfer function (extended intelligent I/O service function: 16 channels maximum) * Low-power consumption (standby mode) * Sleep mode (stops CPU operating clock) * Pseudo-timer mode (stops everything except original oscillation and time-base timer) * Stop mode (stops original oscillation) * CPU Intermittent operation mode * Package * QFP-100 (FPT-100P-M06: 0.65 mm pin pitch) * Process * CMOS technology 1-3
MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1.2 Resources
* I/O port: 26 pins maximum (All 26 pins can also serve as resource pins). * 18-bit time-base timer: 1 channel * Watchdog timer: 1 channel * 16-bit reload timer: 3 channels * 16-bit free-run timer: 1 channel * 16-bit output compare: 1 channel * 16-bit input capture: 2 channels * When the count value of the 16-bit free-run timer matches the setting value of the output compare, the timer is cleared and an interrupt request is issued. * Serial I/O: 2 channels * UART: 2 channels * Clock-synchronous serial transfer (I/O extended serial) can be used. * The direction of the shift clock level can be selected arbitrarily (MSB or LSB). * DTP/external interrupt (4 channels) * Start extended intelligent I/O services by an external input, and generate an external interrupt. * Delayed interrupt generation module * A task-switching interrupt request is generated. * 8-/10-bit A/D converter (16 channel) * 8- or 10-bit resolution can be selected. * FL controller * Enables FL driver control. (The auto display control is performed for 32 digits max. and 59 segments max.) 1 to 32 digits can be set (can be set on a digit-by-digit basis). The dimmer can be set. * Enables LED driver control (Auto display control is performed for 16 segments maximum). The auto display control can be performed for 16 segments max. at 1/2 duty. * Timer clock divider * The original oscillation can be divided by 32, 64, 128, or 256.
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GENERAL
1.3 Product Lineup
Table 1-1 lists the Monolith (MB90M405) series product lineup. Functions other than the ROM/RAM capacity are shared. Table 1-1 MB90M405 Series Product Lineup MB90MV405 MB90MF408 MB90M408 MB90M407 Evaluate Flash Type ROM Mass-produced product (mask ROM) Not provided 128 Kbytes 96 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes Count of basic instructions: 351 Minimum instruction execution time: 59.5 ns (at original oscillation of 4.2 MHz, with PLL clock generated by multiplying original oscillation by 4) CPU Function Addressing types: 23 Program patch function: 2-address pointer Maximum memory space: 16 Mbytes Port I/O port (CMOS) 26 pins (all of 26 pins also serve as resource pins) 60 FL output pins can be used (Under LED control, 43 FL output pins and 17 LED control pins are required). Enables FL driver control and LED driver control can be performed. FL Controller Under FL driver control, the dimmer can be set for both digits and segments. Can also be used as the clock-synchronous method extended I/O serial. Serial I/O (UART) A dedicated baud rate generator is built-in. Four channels are built-in (two channels also serve as UART channels). 16-bit reload timer 16-bit reload timer operation (Toggle output or one-shot output can be selected.) An event count function can be selected. Three channels are built-in. 16-bit free-run timer 16-bit output compare x 1 channel (for clearing free-run timer) 16-bit input capture x 2 channels 8-/10-bit A/D 8-/10-bit resolution x 16 channels (input multiplex) converter Minimum conversion time: 6.2 s (at internal operation of 16 MHz) Timer clock divider The external input clock can be divided and output to the outside. Clock division rates: 16, 32, 64, or 128 (programmable) External interrupt Four independent channels (also serve for A/D input) Interrupt factor: L H edge, H L edge, L level, or H level Low power Sleep mode, stop mode, CPU intermittent mode, or pseudo-timer mode consumption mode Process CMOS Package PGA256 QFP-100 (0.65 mm pitch) Operating voltage 3.3 V 0.3 V(16.8 MHz: 4.2 MHz multiplied by 4) Product name Classification ROM capacity RAM capacity
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MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1.4 Block Diagram
CPU Controller
Timer clock divider 8-/10-bit A/D Converter
ROM (96/128 KB) RAM (4 KB) FL Controller Serial I/O (ch 2) External interrupt input controller
FMC-16LX Bus
FIP17 to FIP59
V-RAM
16-bit input capture (ch 0, 1)
16-bit output compare
Port B Port 8
FIP0/LED0 to FIP16/LED16
Port A
X0,X1 RSTX MD2,1,0
Clock controller
PA0/AN0/TMCK PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7
16-bit free-run timer
PB0/AN8 PB1/AN9 PB2/AN10 PB3/AN11/SI2 PB4/AN12/SC2/TIN PB5/AN13/SO2/TO PB6/AN14/INT3 PB7/AN15/INT2
16-bit reload timer (ch 0, 1, 2) Serial I/O (ch 3) UART (ch.0,1)
P90/SDA/SO3 P91/SCL/SC3
I C Interface
2
P80/IC0/INT0 P81/IC1/INT1 P82/SI0 P83/SC0 P84/SO0 P85/SI1 P86/SI2 P87/SI3
Port 9
Fig. 1.1 Block Diagram (MB90M405)
1-6
GENERAL
1.5 Pin Assignment
FPT-100P-M06 Pin Assignment
FIP15/LED15 100 FIP14/LED14 99 FIP13/LED13 98 FIP12/LED12 97 FIP9/LED9 FIP10/LED10 95 94
FIP11/LED11 96
FIP8/LED8 93
FIP7/LED7 92
FIP6/LED6 91
FIP5/LED5 90
FIP4/LED4 89
FIP3/LED3 88
FIP2/LED2 87
FIP1/LED1 86
FIP0/LED0 85
VCC-CPU 84
VSS-CPU 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB7/AN15/INT3 PB6/AN14/INT2 PB5/AN13/SO2/TO0 RSTX PB4/AN12/SC2/TIN0 PB3/AN11/SI2 PB2/AN10 PB1/AN9 PB0/AN8 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0/TMCK AVSS AVCC P91/SCL/SC3 P90/SDA/SO3 P87/SO1 P86/SC1 P85/SI1 P84/SO0 P83/SC0 P82/SI0 P81/IC1/INT1 P80/IC0/INT0 MD2
X1 83
X0 82
FIP16/LED16 FIP17 FIP18 FIP19 FIP20 FIP21 FIP22 FIP23 FIP24 FIP25 VSS-IO FIP26 FIP27 FIP28 FIP29 FIP30 FIP31 FIP32 FIP33 FIP34 FIP35 FIP36 VDD-FIP FIP37 FIP38 FIP39 FIP40 FIP41 FIP42 FIP43
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FIP44 32 FIP45 33 FIP46 34 FIP47 35 FIP48 36 FIP49 37 FIP50 38 FIP51 39 FIP52 40 FIP53 41 FIP54 42 VSS-IO 43 FIP55 44 FIP56 45 FIP57 46 FIP58 47 FIP59 48 VKK 49 MD0 50 MD1/VDD-VFT
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MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1.6 Pin Description
Tables 1-2, 1-3 and 1-4 list the pin name, function, circuit type, and reset-time state/function. Table 1-2 Pin Description
Pin No. QFP-100M06 82, 83 77 85 to 100 1 2 to 10 12 to 19 20 to 22 24 to 41 43 to 47 Pin Name X0, X1 RSTX FIP0 to FIP15 LED0 to LED15 FIP16 LED16 FIP17 to FIP33 Circuit Type A B State/function at reset Oscillation state Reset input Oscillation input pins. External reset input pin This function is selected when the FL driver is enabled. This function is selected when the LED driver is enabled. This function is selected when the FL driver is enabled. This function is selected when the LED driver is enabled. Function
C VKK Pull-down output
Dedicated pins for the FL driver output. FIP34 to FIP59 P80 D General-purpose I/O port External trigger input pin for input capture 0 External factor input pin for external interrupt input 0 This pin is only accepted when it is enabled by the EN0 bit. General-purpose I/O port External trigger input pin for input capture 1 External factor input pin for external interrupt input 1 This pin is only accepted when it is enabled by the EN1 bit. General-purpose I/O port Serial data input pin for serial I/O channel 0 This pin is always effective when channel 0 is under input operation. General-purpose I/O port Serial clock I/O pin for serial I/O channel 0 This pin is effective when the channel-0 clock output is enabled. General-purpose I/O port Serial data output pin for serial I/O channel 0 This pin is effective when the channel-0 serial data output is enabled. General-purpose I/O port Serial data input pin for serial I/O channel 1 This pin is always effective when channel 0 is under input operation. General-purpose I/O port Serial clock I/O pin for serial I/O channel 1 This pin is effective when the channel-0 clock output is enabled. This pin is a general-purpose I/O port. Serial data output pin for serial I/O channel 1 This pin is effective when the channel-0 serial data output is enabled. General-purpose I/O port (However, the N ch is open drain.) Data I/O pin for the I2C interface. This function is effective when operation of the I2C interface is enabled. Also, set the port output to the Hi-Z state when operating the I2C interface. Serial data output pin for serial I/O channel 3 This pin is effective when the channel-3 serial data output is enabled.
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IC0 INT0 P81 IC1 INT1 P82
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54
SI0 P83
55
SC0 P84
56 SO0 P85 57 SI1 P86 58 SC1 P87 59 SO1 P90 SDA 60 SO3 G Hi-Z
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GENERAL
Table 1-3 Pin Description
Pin No. QFP-100M06 Pin Name P91 Circuit Type State/function at reset Function General-purpose I/O port (However, the N ch is open drain.) 2 Clock I/O pin for the I C interface 2 This function is effective when operation of the I C interface is enabled. 2 Also, set the port output to the Hi-Z state when operating the I C interface. Serial clock I/O pin for serial I/O channel 3 This pin is effective when the channel-3 clock output is enabled. General-purpose I/O port Analog input pin 0 for the A/D converter This function is effective when the analog input specification is enabled (using ADER). Timer clock output pin This pin is only effective when output is enabled. This pin is null when analog input is enabled using ADER. General-purpose I/O port Analog input pins (1 to 10) for the A/D converter This function is effective when the analog input specification is enabled (using ADER). General-purpose I/O port Analog input pin (11) for the A/D converter This function is effective when the analog input specification is enabled (using ADER). Serial data input pin for serial I/O channel 2 This pin is always effective when channel 2 is under input operation. General-purpose I/O port Analog input pin (12) for the A/D converter This function is effective when the analog input specification is enabled (using ADER). Serial clock I/O pin for serial I/O channel 2 This pin is effective when the channel-2 clock output is enabled. External clock input pin for reload timer channel 0 This pin is enabled when the external clock input is effective (ADER takes precedence). General-purpose I/O port Analog input pin (13) for the A/D converter This function is effective when the analog input specification is enabled (using ADER). Serial data output pin for serial I/O channel 2 This pin is effective when the channel-2 serial data output is enabled. External event output pin for reload timer channel 0 This pin is effective when the external event output is enabled (ADER takes precedence). General-purpose I/O port Analog input pins (14, 15) for the A/D converter This function is effective when the analog input specification is enabled (using ADER). External factor input pins for external interrupt inputs 2 and 3 These pins are accepted only when they are enabled using the EN2 bit and the EN3 bit. H -- Vcc power input pin for the analog macro Power input Vss power input pin for the analog macro Power pin on the pull-down side at high-voltage withstand output.
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SCL
G
Hi-Z
SC3 PA0 AN0 64 TMCK PA1 to PB2 65 to 74 AN1 to AN10 PB3 AN11 75 SI2 PB4 AN12 76 F SC2 TIN0 PB5 AN13 78 Analog input
SO2
TO0 PB6 and PB7 AN14 and AN15 79, 80 INT2 and INT3 62 63 48 AVCC AVSS VKK
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MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
Table 1-4 Pin Description
Pin No. QFP-100M06 49 50 51 11, 42 23 81 84 Pin Name Circuit Type State/function at reset Function Input pin for specifying the operating mode Connect this pin to Vcc. Also, always switch this pin to Vss at boot programming to flash memory. Input pin for specifying the operating mode Connect this pin to Vcc. This pin also serves as the VDD-VFT pin. Input pin for specifying the operating mode Connect this pin to Vss. Also, always switch this pin to Vcc at boot programming to flash memory. Power (0 V: GND) input pins for I/O Power (3 V: Vcc) input pin for the FIP Power (0 V: GND) input pin for the controller Power (3 V: Vcc) input pin for the controller
MD0 MD1/VDD-VFT MD2 VSS-IO VDD-FIP VSS-CPU VCC-CPU B Mode pin
--
Power input
1-10
GENERAL
1.7 I/O Circuit Type
Tables 1-5 and 1-6 show the circuit type for each pin. Table 1-5 I/O Circuits
Classification Circuit Remarks * Oscillator * Oscillation feedback resistor: about 1 M
X1 Xout
A
X0
Standby control signal * * R Hysteresis input pin Resistor value: about 50 k (TYP)
B
* P-ch open-drain output - High-voltage withstand port output IOL = -25 mA Pout When using the pin as a normal port, connect a diode clamp, etc., to prevent application of VKK voltage to the pin at output of the L level (see Handling notes).
C
RKK VKK
* P-ch open-drain output - High-voltage withstand port output IOL = -12 mA Pout
D
RKK VKK
When using the pin as a normal port, connect a diode clamp, etc., to prevent application of VKK voltage to the pin at output of the L level (see Handling notes).
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MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
Table 1-6 I/O Circuits
Classification Circuit Remarks * CMOS hysteresis I/O pin * CMOS-level output * CMOS Hysteresis input (The input cutoff function is provided in the standby mode.) IOL = 4 mA
Pout
E
R
Nout
Hysteresis input Standby control * Analog/CMOS hysteresis I/O pin * CMOS-level output * CMOS hysteresis input (The input cutoff function is provided in the standby mode.) * Analog input (Analog input is effective when the corresponding bit of ADER is 1.) IOL = 4 mA
Pout
Nout
F
R Hysteresis input Standby control Analog input
Nout
* N-ch open drain output * CMOS Level hysteresis input (The input cutoff function is provided in the standby mode.) Unlike the CMOS I/O pin, there is no P-ch transistor at this pin. Consequently, even when an external voltage is applied to this pin with the power to the device set to OFF, no current flows to the device power (Vcc-IO/Vcc-CPU).
G
R Hysteresis input Standby control
* Analog power input protector
H
IN
1-12
GENERAL
1.8 Notes on Handling Devices
(1) Be careful not to exceed the maximum rated voltage (Prevention of latch up). For a CMOS IC, latch-up may occur if a voltage higher than Vcc or a voltage lower than Vss is applied to the I/O pin other than medium-/high-voltage withstand I/O pins, or when a voltage that exceeds the rated voltage is applied between Vcc and Vss. Latch up rapidly increases the power current, and the device may be destroyed by heat. When using the device, take care not to exceed the maximum rating. Also, take care that the analog power (AVcc) and the analog input do not exceed the digital power (Vcc) when turning the AC/DC power on or off. (2) Design the device so the supply voltage is as stable as possible. A sudden change in the power voltage may cause a malfunction even within the operating assurance range of the VCC power supply voltage. For safety, the VCC ripple (p-p) of the commercial frequency (50/60 MHz) must be 10% or less of the standard VCC value, and the transient fluctuation at instantaneous power switching must be 0.1 V/ms or less. Also, take countermeasures to power noise, etc. (3) Notes at power-on The voltage rise time at power-on must be 50 s or more (0.2 to 2.7 V). (4) Setting unused input pins Leaving unused input pins open may cause a malfunction. Therefore, these pins must be set to the pullup or pull-down state. (5) Handling of power pins for A/D converter Even when the A/D converter is not used, connect the pins so that the following relationships are established: AVCC = VCC, AVSS = VSS. (6) Notes on using external clock Even when an external clock is used, the oscillation stabilization wait time is required at the power-on reset or the cancellation of the stop mode. In this case, drive the X0 pin only and leave the X1 pin open. Example of using external clock X0 OPEN X1 MB90M405 Series
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MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
(7) Power pins When two or more Vcc pins and Vss pins are provided, pins are designed to be at the same electric potential are internally connected to the device to prevent malfunctions such as latch-up. However, always connect all same electric potential pins to power and ground outside the device to prevent decrease of extraneous and radiation the malfunction of the strobe signal due to a ground level rise, and follow the standards on total output current, etc. Also, consider to connecting the pins to Vcc and Vss of this device at the lowest possible impedance from the current supply source (It is recommended to connect a bypass capacitor of about 0.1 F of the device between Vcc and Vss). (8) Application sequence for power analog inputs for A/D converter Apply the digital power (Vcc) first, and then apply the power (AVcc) and analog inputs (AN0 to AN15) for the A/D converter. Disconnect the power and analog inputs for the A/D converter first, and then disconnect the digital power (Vcc). Also, do not allow the input voltage to exceed AVcc even when using a pin shared with an analog input as an input port (Simultaneous application and disconnection of analog power and digital power is allowed). (9) Output of high-voltage withstand output pin (circuit type C or D) When the high-voltage withstand output pin (circuit type is C or D) is used as an ordinary output port, the port outputs the VKK pin voltage pull-down value at the L level output. In this case, the VKK pin level voltage is applied to the external circuit, so it is recommended to add a diode clamp circuit as shown in the figure below.
Diode clamp circuit Pout
RKK VKK
1-14
GENERAL
1.9 Clock Supply Map
The clock supply map for this device (Monolith: MB90M405) is shown below.
Timer clock divider Clock generator Watchdog timer X0 Oscillator X1 Time-base timer Selector Resources FL Controller 16-bit reload timer 10-bit A/D converter 8-bit serial I/O 6-bit free-run timer 16-bit input capture 16-bit output compare I2C Communications interface
1
2
3
4
PLL Multiplication circuit PCLK Divide-by-2 circuit HCLK MCLK Selector
CPU (F2MC-16LX) ROM/RAM (memory)
HCLK: Oscillation clock MCLK: Main clock (operating clock: clock generated by dividing oscillation clock by 2) PCLK: PLL clock
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MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1.10
This section provides an overview of the low power consumption mode. The onolith (MB90M405) has the following modes that stop various functions and clocks Chapter 4. * Relationships between operating modes and power
Operating mode PLL Run Main Run PLL Sleep Main sleep Pseudo-time Stop Main clock Operates Operates Operates Operates Operates Stops PLL Clock Operates Stops Operates Stops Stops Stops CPU Operates Operates Stops Stops Stops Stops Resources Operates Operates Operates* Operates* Stops Stops Timer clock Operates Operates Operates Operates Operates Stops
In the above table, the power consumption decreases as the operating mode goes down from the top of the table. In the PLL Run mode, operation is performed on the PCLK generated by multiplying the original oscillation by 1 to 4. In the Main Run mode, operation is performed on the MCLK generated by dividing the original oscillation by 2. *: In the sleep mode, the CPU stops, so resources cannot be accessed from the CPU.
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May 19, 2000 Preliminary Version 1 Data sheet
MB90M405 Series
Electric Specification Table
s Electrical Characteristics
1. Absolute Maximum Rating
(VSS-CPU = VSS-IO = AVss = 0.0 V)
Rated Value Parameter Symbol Min. VCC-CPU VDD-FIP Power supply voltage AVCC VKK VI Input voltage *I2 VO Output voltage VO2 "L" level max. output current "L" level avg. output current "L" level max. overall output current "L" level avg. overall output current IOL IOLAV IOL IOLAV IOH "H" level max. output current IOHFIP1 IOHFIP2 "H" level avg. output current "H" level max. overall output current "H" level avg. overall output current IOHAV IOH IOHAV IOHFIPAV PD_CPU Power consumption PD_FL Operating temperature Storage temperature TA TSTG -- -40 -55 1176 +85 +150 mW C C Vss - 0.3 -- -- -- -- -- -- -- -- -- -- -- -- Vss + 5.5 15 4 100 50 -15 -27 -14 -4 -100 -50 -180 300 V mA mA mA mA mA mA mA mA mA mA mA mW Vss - 0.3 Vss - 0.3 Vss + 5.5 Vss + 4.0 V V VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 45 Vss - 0.3 Max. VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.3 Vss + 4.0 V V V V V Power supply pin for control circuit Power supply pin for FIP Vcc > AVcc*
1
Unit
Remarks
Pull-down side power supply pin for high voltage resistance output. * * *
2 3 2
*
* (Open drain output) * ,*
4 5
Average value (Operating current x 5 Operating rate) * *
5
Average value (Operating current x 5 Operating rate) * * ,*
4 5
FIP00 to FIP33 pins FIP34 to FIP59 pIns Average value (Operating current x 5 Operating rate) * *
5
Average value (Operating current x 5 Operating rate) * Average value (Operating current x 6 Operating rate) *
For CPU_Chip individual operation For FL_Chip individual output operation
1
*1: *2: *3: *4: *5: *6:
AVCC should not exceed VCC when turning on the power supply. VI and VO should not exceed VCC + 0.3 V. The 5 V withstandable voltage pin for I C. Applies to P90/SDA, P91/SCL only. The maximum output current is standard at the peak value of the corresponding 1 pin. Excludes currents on the FIP00 to FIP59 pins. FIP00 to FIP59 pins are targeted. 1. The VCC specification in the table means: VDD-FIP = VDD-VFT = VCC-CPU. Use with the same power supply level as the three pins described above. Also, VSS means: VSS-IO = VSS-CPU. Connect this pin to the GND. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltage to this high impedance circuit.
2
Cautions:
2
2. Recommended Conditions
(VSS-IO = VSS-CPU = AVss = 0.0 V)
Rated value Parameter Symbol Min. VCC-CPU Power supply voltage VDD-FIP Vcc VIHS "H" level input voltage VIHS2 VIHM VILS "L" level input voltage VILS2 VILM Operation temperature TA 3.0 3.0 2.5 0.8 Vcc 0.8 Vcc Vcc - 0.3 Vss - 0.3 Vss - 0.3 Vss - 0.3 -40 Max. 3.6 3.6 3.6 Vcc + 0.3 5.8 Vcc + 0.3 0.2 Vcc 0.2 Vcc Vss + 0.3 +85 V V V V V V V V V C Under normal operation Under normal operation Maintains status of stop operation CMOS Hysterisis input pins other than I C CMOS Hysterisis input pins of I C (5 V 1 withstandable voltage)* MD pin input CMOS Hysterisis input pins other than I C CMOS Hysterisis input pins of I C (5 V 1 withstandable voltage)* MD pin input
2 2 2 2
Unit
Remarks
*1:
On the 1st ES product of MB90MF408, the withstandable voltage is 3 V (can be used up to 4.5 V at the test lab level). The VCC specification in the table means: VDD-FIP = VDD-VFT = VCC-CPU. Use with the same power supply level as the three pins described above. Also, VSS means: VSS-IO = VSS - CPU. Connect this pin to the GND.
Caution:
3
3. DC Specifications
(TA = -40 to 85C, VDD-FIP = VDD-VFT = VCC-CPU = AVCC = 3.0 to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V)
Rated value Parameter Symbol Pin Test Condition Min. VOH5 VOH4 VOH3 Output H voltage VOH2 VOH1 VCC = 3.3 V IOH5 = -23 mA VCC = 3.3 V IOH4 = -12 mA VCC = 3.3 V IOH3 = -12 mA VCC = 3.3 V IOH2 = -5 mA IOH1 = -4 mA Vcc - 2.5 Vcc - 1.3 Vccv - 2.0 Vcc - 1.0 -- Vcc - 0.5 -- Typ. -- -- -- -- -- Vcc- 0.3 0.5 Max. -- -- -- -- 5.5 V V V V V Open drain pin *
2
Unit
Remarks
FIP00 to FIP33
FIP34 to FIP59 SDA/SCL All output pins other than the above SDA/SCL All output pins other than the above Input pins other than FIP00-59 FIP00 to FIP33 FIP34 to FIP59
VOH0
IOH = -2.0 mA
--
V
VOL1 Output L voltage
IOL = 15 mA
0.8
V
VOL
IOL = 2.0 mA
--
0.2
0.4
V
Input leak current
IIL
VCC = 3.0 V
( VS*-5
-1
5
A A A MB90M407/8 (argeted standard 1 values)* MB90M407/8 (targeted standard 1 values)* MB90MF408 MB90MV405 (F targeted standard 1 values)* MB90MF408
ILO3 Output leak current ILO2
VCC = 3.3 V
(VCC - 43-- --
-- --
20 10
VCC = 3.3 V
(VCC- 43Vcc = 3.3 V, and internal operation at 16 MHz, and normal operation Vcc = 3.3 V, and internal operation at 16 MHz, and A/D operation Vcc = 3.3 V, and internal operation at 16 MHz, and normal operation Vcc Vcc = 3.3 V, and internal operation at 16 MHz, and A/D operation Flash programming/erasing Vcc = 3.3 V, and internal operation at 16 MHz, and sleep operation
--
32
40
mA
--
37
45
mA
ICC Power supply current
--
40
50
mA
MB90MV405 -- 45 55 mA (F targeted standard 1 values)* MB90MF408
--
40
50
mA
ICCS
--
15
20
mA
*
1
(Continue)
4
(Continued) Rated value Parameter Symbol Pin Test Condition Min. Power supply current Pull-up resistor Pull-down resistor ICCH TA = +25C, and operation stopped RSTX MD2 FIP00 to FIP59 -- -- When there are settings -- Typ. 15 Max. 20 A (Targeted standard values) Unit Remarks
RUP RDW1 RDW1
20 20 80
65 65 120
200 200 160
k k k
*1: *2: Notes:
Current values that are specified do not include the consumption current on the high withstandable voltage pins. They indicate the consumption current internally on the circuit. On the 1st ES product of MB90MF408, the Max. standard value is 3.6 V (can be used up to 4.5 V at the test lab level). 1. The VCC specification in the table means: VDD-FIP = VDD-VFT = VCC-CPU. Use with the same power supply level as the three pins described above. Also, VSS means: VSS-IO = VSS - CPU. Connect this pin to the GND. 2. There can be changes in the current value according to improvements in performance. The measuring condition of the power supply current is the external clock.
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* PLL operating guaranteed range Relationship between internal-operation clock frequency and power supply voltage
PLL operating guaranteed range 3.6 Power supply voltage Vcc (V)
3.0
1.5
3 Internal Clock fCP(MHz)
16
Relationship between original oscillation frequency and internal-operation clock frequency
16 Internal clock fCP (MHz)
4 multipulation 3 multipulation
2 multipulation
1 multipulation
12 9 8 6 4 3 2 1.5 3 4 6 8 12 16
Nonmultipulation
Original Oscillating Clock fCP (MHz)
6
4.
A/D Conversion Unit Electrical Characteristics
(TA = -40 to +85C, VCC-CPU AVcc = 3.0 V to 3.6 V, VSS-CPU = VSS-IO = AVss = 0 V)
Rated value Parameter Symbol Pin Min. Typ. -- -- -- -- A*ss +0.5 LSB AVcc -1.5 LSB -- -- -- -- -- -- -- -- 100 -- -- Max. 10 3.0 2.5 1.9 Avss +2.5 LSB Avcc +0.5 LSB -- -- -- 10 AVcc AVcc 5 5 200 5 4 bit LSB LSB LSB mV 1LSB= AVcc/1022 mV ns ns ns A V V mA A A A LSB *
1
Unit
Remarks Can switch to 8 bits
Resolution Overall error Non-linearity error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time (Sampling + Compare) Sampling time Compare time Analog port input current Analog input voltage Reference voltage Power supply current
-- -- -- -- V OT VFST -- -- -- IAIN VAIN -- IA IAH
-- -- -- -- AN0 to AN15 AN0 to AN15 -- -- -- AN0 to AN15 AN0 to AN15 AVcc AVcc AVcc AVcc AVcc AN0 to AN15
-- -- -- -- Avss -1.5 LSB AVcc -3.5 LSB 98 tCP * 32 tCP * 66 tCP * -- 0 3.0 -- -- -- -- --
2
16 MHz operation 16 MHz operation 16 MHz operation
2 2
*
1
Reference voltage supply current Channel differences
IR IRH --
When not operating A/D converter, this is the current (VCC-CPU = AVCC = 3.3 V) when the CPU is stopped. *2: tCP means: 1/internal operating frequency. When the internal operating frequency is 16 MHz, tCP is 1/16 MHz = 62.5 ns. 1. The reference L value is fixed at AVSS; the reference H value is fixed at AVCC. Notes: The error is relatively large as the AVCC becomes smaller. 2. Analog input external circuit output impedance should use the following conditions. External Circuit Output Impedance 10 k 3. If the external circuit output impedance is too high, there maybe insufficient time for sampling of the analog voltage.
*1:
* Analog input circuit model diagram
RON
C Comparator
Analog input MB90M407/M408 R= About 1.5 k ON C= About 30 pF MB90MF408, MB90MV405 R = About 3.0 k ON C = About 65 pF
Note: Numeric values herein should be used as a guide.
7
6. Handling Device
* Preventing latch-up Latch-up may occur in CMOSIC when a voltage higher than VCC-CPU or lower than VSS-CPU is applied to the input or output pins, or a voltage exceeding the rated value is applied between V CC-CPU and VSS-CPU. Latchup may cause a rapid increase in the supply current, sometimes resulting in thermal damage to the device. Therefore, keep the used voltage within the maximum ratings. When turning the power on and off the analog supply voltage (AVCC) analog input should not exceed the digital supply voltage (VCC-CPU). * Voltage supplies should be stabilized. A sudden change of the power supply voltage may cause a malfunction even within the guaranteed range of operation of the VCC-CPU power supply voltage. For reference of stabilization, voltage variations are recommended to be restrained so that VCC-CPU ripple variations (P-P values) are below 10% of the standard V CC-CPU value in commercial frequencies (50 to 60 Hz), and so that transient variation is below 0.1 V/ms in sudden changes during power switchovers. * Precautions when turning on the power supply Ensure a minimum of 50 s (between 0.2 to 2.7 V) for voltage rise times when turning on the power supply to prevent malfunction of the built-in power reduction circuit. * Handling of unused input pins Leaving unused input pins open may cause a malfunction. Therefore, these pins should be connected to a pull-up or a Pull-down resistor. * Handling of A/D converters power supply pins Connect power supply pins with AVCC = VCC-CPU, AVSS = VCC-IO even when not using the A/D converters. * Precautions when using the external clock Oscillating stability waiting time is required when resetting from the Power On Reset, Stop Mode when using the external clock. * Order of turning on the power Turn off the digital power supply (VCC-CPU) after turning off the A/D converter power supplie (AVCC, AVSS) and analog input (AN0 to AN15). Do not allow the input voltage to exceed AVCC when using the analog input pins as an input port.
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